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MC74VHCT373A Octal D-Type Latch with 3-State Output
The MC74VHCT373A is an advanced high speed CMOS octal latch with 3-state output fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. This 8-bit D-type latch is controlled by a latch enable input and an output enable input. When the output enable input is high, the eight outputs are in a high impedance state. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The VHCT inputs are compatible with TTL levels. This device can be used as a level converter for interfacing 3.3 V to 5.0 V, because it has full 5.0 V CMOS level output swings. The VHCT373A input and output (when disabled) structures provide protection when voltages between 0 V and 5.5 V are applied, regardless of the supply voltage. These input and output structures help prevent device destruction caused by supply voltage-input/output voltage mismatch, battery backup, hot insertion, etc.
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MARKING DIAGRAMS
20 VHCT373A AWLYYWWG 1
1
SOIC-20WB SUFFIX DW CASE 751D
20 VHCT 373A ALYWG G 1
* * * * * * * * * * * *
High Speed: tPD = 7.7 ns (Typ) at VCC = 5.0 V Low Power Dissipation: ICC = 4 mA (Max) at TA = 25C TTL-Compatible Inputs: VIL = 0.8 V; VIH = 2.0 V Power Down Protection Provided on Inputs and Outputs Balanced Propagation Delays Designed for 4.5 V to 5.5 V Operating Range Low Noise: VOLP = 1.6 V (Max) Pin and Function Compatible with Other Standard Logic Families Latchup Performance Exceeds 300 mA ESD Performance: Human Body Model > 2000 V; Machine Model > 200 V Chip Complexity: 196 FETs or 49 Equivalent Gates Pb-Free Packages are Available*
1
TSSOP-20 SUFFIX DT CASE 948E
A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G or G = Pb-Free Package (Note: Microdot may be in either location)
FUNCTION TABLE
INPUTS OE L L L H LE H H L X D H L X X OUTPUT Q H L No Change Z
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet.
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2006
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January, 2006 - Rev. 4
Publication Order Number: MC74VHCT373A/D
MC74VHCT373A
3 4 7 8 13 2 5 6 9 12 15 16 19 OE Q0 D0 NONINVERTING OUTPUTS D1 Q1 Q2 D2 D3 Q3 GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC Q7 D7 D6 Q6 Q5 D5 D4 Q4 LE
DATA INPUTS
D0 D1 D2 D3 D4
14 D5 17 D6 18 D7 LE OE 11 1
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
Figure 1. Logic Diagram
Figure 2. Pin Assignment
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MAXIMUM RATINGS
Symbol VCC Vin Parameter Value Unit V V V DC Supply Voltage DC Input Voltage - 0.5 to + 7.0 - 0.5 to + 7.0 Vout IIK DC Output Voltage Outputs in 3-State High or Low State - 0.5 to + 7.0 - 0.5 to VCC + 0.5 - 20 20 25 75 500 450 Input Diode Current mA mA mA mA IOK Iout Output Diode Current (VOUT < GND; VOUT > VCC) DC Output Current, per Pin ICC PD DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Storage Temperature SOIC Packages TSSOP Package mW _C Tstg - 65 to + 150 Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. Derating - SOIC Packages: - 7 mW/_C from 65_ to 125_C TSSOP Package: - 6.1 mW/_C from 65_ to 125_C
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V CC ). Unused outputs must be left open.
RECOMMENDED OPERATING CONDITIONS
Symbol VCC Vin Parameter Min 4.5 0 0 0 Max 5.5 5.5 Unit V V V DC Supply Voltage DC Input Voltage
Vout TA
DC Output Voltage
Outputs in 3-State High or Low State
5.5 VCC
Operating Temperature
- 40 0
+ 85 20
_C
tr, tf
Input Rise and Fall Time
VCC =5.0V 0.5V
ns/V
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1. Parameter guaranteed by design. tOSLH = |tPLHm - tPLHn|, tOSHL = |tPHLm - tPHLn|. 2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC / 8 (per latch). CPD is used to determine the no-load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC.
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AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns) DC ELECTRICAL CHARACTERISTICS
Symbol Symbol tOSLH, tOSHL tPLH, tPHL tPLH, tPHL tPLZ, tPHZ tPZL, tPZH IOPD ICCT VOH Cout VOL VIH ICC IOZ Cin VIL Iin Power Dissipation Capacitance (Note 2) Maximum Three-State Output Capacitance (Output in High-Impedance State) Maximum Input Capacitance Output to Output Skew Output Disable Time, OE to Q Output Enable Time, OE to Q Maximum Propagation Delay, D to Q Maximum Propagation Delay, LE to Q Output Leakage Current Quiescent Supply Current Maximum Quiescent Supply Current Maximum 3-State Leakage Current Maximum Input Leakage Current Maximum Low-Level Output Voltage Vin = VIH or VIL Minimum High-Level Output Voltage Vin = VIH or VIL Maximum Low-Level Input Voltage Minimum High-Level Input Voltage Parameter Parameter VOUT = 5.5V Per Input: VIN = 3.4V Other Input: VCC or GND Vin = VCC or GND Vin = VIL or VIH Vout = VCC or GND Vin = 5.5 V or GND IOL = 8mA IOL = 50mA IOH = - 8mA IOH = - 50mA Test Conditions VCC = 5.5 0.5V (Note 1) VCC = 5.0 0.5V RL = 1kW VCC = 5.0 0.5V RL = 1kW VCC = 5.0 0.5V VCC = 5.0 0.5V
CPD
MC74VHCT373A
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Test Conditions CL = 50pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF 4.5 to 5.5 4.5 to 5.5 0 to 5.5 VCC V 5.5 5.5 5.5 4.5 4.5 4.5 4.5 0 3.94 Min Min 4.4 2.0 TA = 25C TA = 25C Typical @ 25C, VCC = 5.0V Typ Typ 8.8 6.3 7.1 5.1 5.9 7.7 8.5 0.0 4.5 6 4 0.25 0.1 10.9 11.9 12.3 13.3 Max 1.35 0.36 Max 11.2 1.0 8.5 9.5 0.5 4.0 0.1 0.8 10 25 TA = - 40 to 85C TA = - 40 to 85C 3.80 Min Min 1.0 1.0 1.0 1.0 1.0 1.0 1.0 4.4 2.0 2.5 1.0 12.0 12.5 13.5 9.5 10.5 13.5 14.5 Max 1.50 40.0 0.44 Max 1.0 5.0 0.1 0.8 10 Unit Unit mA mA mA mA mA pF pF pF ns ns ns ns ns V V V V
3
MC74VHCT373A
NOISE CHARACTERISTICS (Input tr = tf = 3.0ns, CL = 50 pF, VCC = 5.0V)
TA = 25C Symbol VOLP VOLV VIHD VILD Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Minimum High Level Dynamic Input Voltage Maximum Low Level Dynamic Input Voltage Parameter Typ 1.2 -1.2 Max 1.6 -1.6 2.0 0.8 Unit V V V V
TIMING REQUIREMENTS (Input tr = tf = 3.0ns)
TA = 25C Symbol tw(h) tsu th Parameter Minimum Pulse Width, LE Minimum Setup Time, D to LE Minimum Hold Time, D to LE Test Conditions VCC = 5.0 0.5 V VCC = 5.0 0.5 V VCC = 5.0 0.5 V Typ Limit 6.5 1.5 3.5 TA = - 40 to 85C Limit 8.5 1.5 3.5 Unit ns ns ns
ORDERING INFORMATION
Device MC74VHCT373ADWR2 MC74VHCT373ADWRG MC74VHCT373ADTR2 MC74VHCT373ADTRG Package SOIC-20WB SOIC-20WB (Pb-Free) TSSOP-20* TSSOP-20* Shipping 1000 / Tape & Reel 1000 / Tape & Reel 2500 / Tape & Reel 2500 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb-Free.
D tPLH Q
1.5V tPHL 1.5V
3V GND VOH VOL
tw LE 1.5V tPLH Q 1.5V tPHL
3V GND
VOH VOL
Figure 3. Switching Waveform
Figure 4. Switching Waveform
3V OE 1.5V tPZL Q 1.5V tPZH Q 1.5V tPHZ tPLZ GND HIGH IMPEDANCE VOL +0.3V VOH -0.3V HIGH IMPEDANCE LE D 1.5V tsu th 1.5V VALID 3V GND 3V GND
Figure 5. Switching Waveform
Figure 6. Switching Waveform
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MC74VHCT373A
TEST POINT OUTPUT DEVICE UNDER TEST C L*
*Includes all probe and jig capacitance
Figure 7. Test Circuit
TEST POINT OUTPUT DEVICE UNDER TEST 1 kW CONNECT TO VCC WHEN TESTING tPLZ AND tPZL. CONNECT TO GND WHEN TESTING tPHZ AND tPZH.
C L*
*Includes all probe and jig capacitance
Figure 8. Test Circuit
D0 3 D Q
D1 4 D Q
D2 7 D Q
D3 8 D Q
D4 13 D Q
D5 14 D Q
D6 17 D Q
D7 18 D Q
LE LE 11
LE
LE
LE
LE
LE
LE
LE
OE
1 2 Q0 5 Q1 6 Q2 9 Q3 12 Q4 15 Q5 16 Q6 19 Q7
Figure 9. Expanded Logic Diagram
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MC74VHCT373A
PACKAGE DIMENSIONS
SOIC-20 WB DW SUFFIX CASE 751D-05 ISSUE G
D
A
11 X 45 _
q
H
M
B
M
20
10X
0.25
E
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A A1 B C D E e H h L q MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_
1
10
20X
B 0.25
M
B TA
S
B
S
A
SEATING PLANE
h
18X
e
A1
T
C
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L
MC74VHCT373A
PACKAGE DIMENSIONS
TSSOP-20 D5 SUFFIX CASE 948E-02 ISSUE B
20X
K REF
M
0.15 (0.006) T U
S
0.10 (0.004)
TU
S
V
S
2X
L/2
L
PIN 1 IDENT 1 10
B -U-
J J1
N 0.15 (0.006) T U
S
A -V- N F
C D 0.100 (0.004) -T- SEATING
PLANE
G
H
DETAIL E
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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IIII IIII IIII
SECTION N-N M DETAIL E
20
11
K K1
0.25 (0.010)
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.252 0.260 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
-W-
DIM A B C D F G H J J1 K K1 L M
MC74VHCT373A/D

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